●memtest86+教學 Part13

分頁我想應該是memtest86的精華，若能真的把這部分搞懂，我想對IA32(x86)的認識又進入到更深一層的境界了。若你想對整個IA-32的分頁做作通盤認識你可以去參考Intel 64 and IA-32 Architectures Software Developer's Manual - Volume 3A System Programming Guide.pdf。由於一般書籍講到的分頁都是使用4kbyte的分頁模式，而且只講到CR3（或稱 PDBR，page directory base register），然而IA-32的分頁方式還分成好幾種模式；而且支援4K、2M、4M的分頁大小；並可定址到64G (36-BIT PHYSICAL ADDRESSING USING THE PAE PAGING MECHANISM)；說的好像很複雜，其實就是在搞CR3、CR4這兩個暫存器(register)。然而其實也沒那麼簡單，無論如何，由於memtest86是採用2M分頁(page size extensions)及支援PAE paging mechanism使可定址到64G；因此我們至少要對這種分頁方式作一番說明：

首先我們先來看看爛豬腳(head.S)如何實作頁目錄，你可能會問不是還要有頁表嗎？這個問題非常好但是我不想在此解答，你直接參考我上面說的那份資料以及Paging Extensions for the Pentium Pro Processor 就可知道為何。

在head.S有這麼一段code：注意；在巨集中使用參數必須前面加上"\"符號

.macro ptes64 start, count=64

.quad \start + 0x0000000 + 0xE3 ;為什麼是E3，下面會解說

.quad \start + 0x0200000 + 0xE3

.quad \start + 0x0400000 + 0xE3

.quad \start + 0x0600000 + 0xE3

.quad \start + 0x0800000 + 0xE3

.quad \start + 0x0A00000 + 0xE3

.quad \start + 0x0C00000 + 0xE3

.quad \start + 0x0E00000 + 0xE3

.if \count-1ptes64 "(\start+0x01000000)",\count-1

.endif

.endm

.macro maxdepth depth=1

.if \depth-1maxdepth \depth-1

.endif

.endm

maxdepth

.balign 4096

.globl pd0

pd0: ptes64 0x0000000000000000
.balign 4096

.globl pd1

pd1: ptes64 0x0000000040000000
.balign 4096

.globl pd2

pd2: ptes64 0x0000000080000000
.balign 4096

.globl pd3

pd3: ptes64 0x00000000C0000000
.balign 4096

.globl pdp

pdp:

.long pd0 + 1

.long 0

.long pd1 + 1

.long 0
.long pd2 + 1

.long 0
.long pd3 + 1

.long 0

上面這段code最重要的就是ptes64那個巨集(macro)；若你把pd0:、pd1:、pd2:、pd3:後面的ptes64巨集展開，便會得到0~4GB的頁目錄表，而且每個表項相差2MB。差別在於其每一個頁目錄表項佔用一個quad(8Byte)，這和我之前介紹的那本"自己動手寫作業系統"所談到的分頁採用long為頁目錄，相差4個bytes；-而且書面說的也不搞pdp，原因如下：

Figure 3-21 shows the format for the page-directory-pointer-table and page-directory entries when 2-MByte pages and extended physicaladdresses are being used.

The major differences in these entries are as follows:

•A page-directory-pointer(pdp)-table entry is added.

•The size of the entries are increased from 32 bits to 64 bits

•The maximum number of entries in a page directory or page table is 512.

•The base physical address field in each entry is extended to 24 bits for 36-bit physical addressing (or extended to MAXPHYADDR-12 bits if MAXPHYADDR is different than 36).

另外針對"至少在各式各樣的Pentium簡介中有四個2M頁[1,2,3,4]"這句話的意思，答案如下：

Figure 3-19 shows how a page-directory-pointer table and page directories can be used to map linear addresses to 2-MByte pages when the PAE paging mechanism enabled. This paging method can be used to map up to 2048 pages (4 page-directory-pointer(pdp)-table entries times 512 page-directory entries) into a 4-GByte linear address space.也就是Figure 3-19中的bit30和bit31。

/*-----------------參考init.c map_page()--------------- *

0xE3 --

* Bit 0 = Present bit. 1 = PDE is present

* Bit 1 = Read/Write. 1 = memory is writable

* Bit 2 = Supervisor/User. 0 = Supervisor only (CPL 0-2)

* Bit 3 = Writethrough. 0 = writeback cache policy

* Bit 4 = Cache Disable. 0 = page level cache enabled

* Bit 5 = Accessed. 1 = memory has been accessed.

* Bit 6 = Dirty. 1 = memory has been written to.

* Bit 7 = Page Size. 1 = page size is 2 MBytes

* --------------------------------------------------*/

透過以上的認知我們要來看其他的code如何來實作分頁‧‧‧待續‧‧‧